Every DSP or FPGA application has varying input and output requirements. These can be simple USB interfaces, CameraLink, or high-speed analog I/O. Utilising a standard base module, a flexible system can be tailored by attaching a wide variety of daughter modules. For this reason, the SLB mezzanine concept was introduced.
This concept consists of a carrier board (often a DSP or FPGA TIM module) which includes a high density connector. This connector accepts a daughter module (or mezzanine) which is mounted above the carrier (or in some case can be mounted separately and joined using a flexible cable).
The SLB connector is of a differential construction (based on a Samtec QSH/QTH-DP series 0.5mm pitch connectors) and characterised for high-speed data of over 1Gb/s per pin pair.
The connector is split into three sections, 2 for high-speed differential (LVDS) data transfer, and one for control. A separate connector provides power to the mezzanine board.
Below are listed the features of the SLB:
- Low Voltage Differential Signalling (LVDS), supported by Xilinx FPGAs,
- One control signal port,
- Two differential data ports,
- A set of power supplies: +3.3, +5, +12 and –12 Volts.
- Two-extra mounting holes to hold Main/Base and Daughter modules together.
Full information about the SLB Standard can be found in the SLB (Sundance Local Bus) Specification (PDF)
Listed below is a table of the I/O voltages for various SLB modules. This table will be updated as and when the information becomes available.
|SLB Module||I/O Level|
|SMT945||2.5V Drive or 2.5V/3.3V Receive|