Christopherh: Created page with "Every DSP or FPGA application has varying input and output requirements. These can be simple USB interfaces, CameraLink, or high-speed analog I/O. Utilising a standard base mo..."

2015-12-08T11:40:48Z

Created page with "Every DSP or FPGA application has varying input and output requirements. These can be simple USB interfaces, CameraLink, or high-speed analog I/O. Utilising a standard base mo..."

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Every DSP or FPGA application has varying input and output requirements. These can
be simple USB interfaces, CameraLink, or high-speed analog I/O. Utilising a standard
base module, a flexible system can be tailored by attaching a wide variety of daughter
modules. For this reason, the SLB mezzanine concept was introduced.

This concept consists of a carrier board (often a DSP or FPGA TIM module) which
includes a high density connector. This connector accepts a daughter module (or
mezzanine) which is mounted above the carrier (or in some case can be mounted
separately and joined using a flexible cable).

The SLB connector is of a differential construction (based on a Samtec QSH/QTH-DP
series 0.5mm pitch connectors) and characterised for high-speed data of over 1Gb/s per
pin pair.

The connector is split into three sections, 2 for high-speed differential (LVDS) data
transfer, and one for control. A separate connector provides power to the mezzanine
board.

Below are listed the features of the SLB:
* Low Voltage Differential Signalling (LVDS), supported by Xilinx FPGAs,
* One control signal port,
* Two differential data ports,
* A set of power supplies: +3.3, +5, +12 and –12 Volts.
* Two-extra mounting holes to hold Main/Base and Daughter modules together.

Full information about the SLB Standard can be found in the [http://tinyurl.com/slb-specification SLB (Sundance Local Bus) Specification (PDF)]

Listed below is a table of the I/O voltages for various SLB modules.
This table will be updated as and when the information becomes available.

<table border="1" width="300">
<tr>
<th>SLB Module</th>
<th>I/O Level</th>
</tr>
<tr>
<td>SMT350</td>
<td>3.3V</td>
</tr>
<tr>
<td>SMT381</td>
<td>2.5V</td>
</tr>
<tr>
<td>SMT384</td>
<td>3.3V</td>
</tr>
<tr>
<td>SMT390</td>
<td>3.3V</td>
</tr>
<tr>
<td>SMT391</td>
<td>2.5V</td>
</tr>
<tr>
<td>SMT399-160</td>
<td>3.3V</td>
</tr>
<tr>
<td>SMT903</td>
<td>3.3V</td>
</tr>
<tr>
<td>SMT909</td>
<td>2.5V</td>
</tr>
<tr>
<td>SMT911</td>
<td>3.3V</td>
</tr>
<tr>
<td>SMT916</td>
<td>2.5V</td>
</tr>
<tr>
<td>SMT922</td>
<td>2.5V</td>
</tr>
<tr>
<td>SMT939</td>
<td>2.5V</td>
</tr>
<tr>
<td>SMT941</td>
<td>2.5V</td>
</tr>
<tr>
<td>SMT942</td>
<td>2.5V</td>
</tr>
<tr>
<td>SMT943</td>
<td>2.5V</td>
</tr>
<tr>
<td>SMT945</td>
<td>2.5V Drive or 2.5V/3.3V Receive</td>
</tr>
<tr>
<td>SMT946</td>
<td>2.5V</td>
</tr>
<tr>
<td>SMT949</td>
<td>2.5V</td>
</tr>
<tr>
<td>SMT950</td>
<td>3.3V</td>
</tr>
<tr>
<td>SMT959</td>
<td>2.5V</td>
</tr>
</table>

SLB Mezzanine - Revision history

Christopherh: Created page with "Every DSP or FPGA application has varying input and output requirements. These can be simple USB interfaces, CameraLink, or high-speed analog I/O. Utilising a standard base mo..."