EMC2: Difference between revisions

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petalinux-build
petalinux-build


petalinux-package --boot --u-boot --fpga subsystems/linux/hw-description/Name_Of_The_Bitfile.bit --fsbl images/linux/zynq_fsbl.elf --force
petalinux-package --boot --u-boot --fpga subsystems/linux/hw-description/Name_Of_The_Bitfile.bit --fsbl images/linux/zynq_fsbl.elf --force
 
(This step can be created in SDK tools)





Revision as of 17:14, 18 March 2016

1. Q. How to use the EMC2 board properly?

1. Sundance currently support EMC-2-DP-V2 only.

2. The Xilinx Zynq-7000 (Z-7012, Z-7015, and Z-7030) SoM, supported by the Xilinx Vivado tool.

3. When the board is power up the LED light D2 (green) on the Zynq SoM; LEDs (right two) on the Main carrier board and LEDs (top two) on the SEIC module are automatically lit up.

4. The board can be programmed via JTAG (Xilinx platform cable USB) or Flash (SPI or SD card).

5. When the board is being bitstream (programming!), the D2 will be lit off.

6. Before you to make any setting change of the jumpers and DIP switches, please ensure that the board is power off.



2. Q. How to set-up the I/O voltage for the EMC2 board?


The jumper (JP7) and (JP8) are for the voltage(A): SEIC HDMI and voltage(B): FMC respectively.

  3.3V : Position 1-2 
  2.5V : position 2-JP7A and 2-JP8A
  1.8V : Position 2-3



3. Q. How to set-up the Boot Mode for the EMC2 board?


The jumper (JP11) is the boot mode for the "flash devices" to be set from the EMC2.

  QSPI flash mode : Position 1-2   resides on the Zynq MIO 1..6.
  SD card mode : Position 2-3 (closet to JP12)  resides on the Zynq MIO 40..45.



4. Q. How to set-up the Host and Add-on board modes of "PCIe/104" for the EMC2 board?


The jumper (JP12) is installed to configure the EMC2 as the "host mode"; otherwise as "add-on" board mode.

Note: The "add-on" board mode can be separated as stack-up and stack-down mode.


5. Q. How to set-up the Upstream Port for the EMC2 board?


The DIP switch (SW2) is used to set up the “strapping input“ signals to the PCIE/104 for the EMC2.

  (PEX) Port 0 : (Pcie) Lane 0 : 0000(LLLL) : All On
  (PEX) Port 4 : (Pcie) Lane 1 : 0100(LHLL) : On-Of-On-On
  (PEX) Port 1 : (Pcie) Lane 4 : 0001(LLLH) : Of-On-On-On
  (PEX) Port 5 : (Pcie) Lane 5 : 0101(LHLH) : On-Of-On-Of
  (PEX) Port 7 : (Pcie) Lane 6 : 0110(LHHL) : Of-Of-Of-On
  (PEX) Port 9 : (Pcie) Lane 7 : 0111(LHHH) : On-Of-Of-Of

Note: The 4-digit number represents the PEX8606 switch port decimal number. The 0(L) is set to "On" and 1(H) is set to "Of" from the (SW2).


6. Q. What Xilinx Vivado version are supported for the EMC2 development board files and how to installed them?

All the EMC2 board files are well supported from Vivado 2015.2, and we recommend to use the latest version of Vivado.

To installed the EMC2 board files:

1. Download the two files "board_parts" and "board_files"

2. Replace them to where are your Vivado is installed (eg. C:/Xilinx/Vivado/2015.2/data/boards/)



7. Vivado & SDK Design Flow (Quick Tutorial)

Vivado Flow:

1. Create a project as "VHDL" as Target Language and select "EMC-2 Z7015 PCIe/104 modular FPGA platform" as default boards.

2. In the Vivado GUI, click on (Left column) IP Integrator -> Create Block Design, creating your block design, right clicking the "Diagram" terminal and select "Add IP" then add "ZYNQ7 Processing

System" on your diagram.

3. We suggest our customers to load our default Zynq module for the EMC2 TCL commands (zynq_emc2.tcl) and then to extend your customization.

4. Run DRC (F6)

5. Create HDL Wrapper

6. Inserting your design constraints (Some of the deivce I/O constraints are provided by Sundance).

7. Program & Debug -> Generate Bitstream

8. File -> Export -> Export Hardware


SDK Flow:

1. File -> Launch SDK

2. A platform HW will appear on the "Project Explorer".

3. Xilinx Tools -> Repositories , to include your software source codes directory in "Local Repositories" section.

4. File -> New -> Board support package (standalone is used for JTAG) and then to choose the Supported Libraries.

5. File -> New -> Application project (to choose using exiting bsp).

6. Right clicking your "Apps" to click Generate Linker Script.

7. Right clicking your "src" under Apps to import your source codes.

8. Build the project.

9. Connect the UART cable from the board to your host PC; power up the board and "Program FPGA", and right clicking your "Apps" -> Run as -> Launch on Hardware



8. How to create Zynq FSBL (First Stage Boot Loader) for the EMC2?


9. How to create a SD boot and run Petalinux for the EMC2?

1. Following the linux command below:

petalinux-create -t project -n Name_Of_The_Project --template zynq

copy My_Example_Project.hdf into \Name_Of_The_Project\hw-description

cd Name_Of_The_Project\hw-description

petalinux-config --get-hw-description

cd ..

petalinux-build

petalinux-package --boot --u-boot --fpga subsystems/linux/hw-description/Name_Of_The_Bitfile.bit --fsbl images/linux/zynq_fsbl.elf --force (This step can be created in SDK tools)


2. copy boot.bin and \images\linux\image.ub to SD card root



10. UART cables connection problem for the EMC2?

A standard USB mini/micro to USB cable can connect this to a host PC. The UART interface resides on the Zynq MIO 14..15.

If your UART console does not display anything in Xilinx SDK tools:

1. To check your Zynq CPU configuration, the UART0 is enabled Vivado and is connected to MIO 14 and 15.

2. Go to your Windows, Start -> Device Manager -> Port(COM & LPT) to check the list of available ports, and do they also appear on the terminal as you open it for the console?

3. we recommend customer to play the Xilinx 2015.4 Vivado & SDK tools by using Windows 8 OS or further version. (If you using 2015.2 on 'Windows 7, please have installed additional serial console tools, such as "Putty" and "TeraTerm").



11. Xilinx SDSoC supported for the EMC2?