DVIP

Got a customer asking if the DVIP + SMT939 can do realtime processing at 1080p25, 1600x1200@60Hz. The images would be processed by the DM642 and C6455. Can the DM642 support that rate ?

The video IP ports run upto 80Mhz @20bit - there are 3 if you utilise them but I think the 1600x1200 may be pushing it at 162Mhz RGB pixel-rate. As the fpga is mapped to the EMIF @ 100Mhz 64bit I guess that another option. So I guess it will do it but at 60Hz the EMIF bus will be very busy and may not have a huge abount of time left to process. The 1080p25 is more promising - using ITU BT1120 (74.25Mhz) it will be capable of 1080 @ 30P, 25P, 50i, 60i, 25P 24P etc at 4:2:2 YUV 16/20bit. Possibly if you use 2 ports you may get 1080 50P/60P. This can be DMA directly in SDRAM for processing.

Are the following modes supported by the SMT939 : 1080PsF23.98, 1080PsF24, 720p50

As long as the pixel clock frequencies are below the 939 spec - 165Mhz - then it will just spit out the data.

If I understand correctly the output the standard is determined by the control signals and the clock used. Can you describe how the clock should be mapped? Is it supposed to come from the DVI input (which implies that input and output dvi rate have to be the same) or is it to be generated by the FPGA? What clocks are needed for each standard?

If your using the BT1120 standard the clock freq are as above.

You may want to get the customer to spec the standard in case to make sure you have the right res, as these 1920 x 1080 i/25/30 etc are not vesa standards but are HD TV standards which are the BT 1120 I believe - its a bit confusing with the different types.

Clock wise use the input clock to get the data in and store etc - if you need it to output if there is no input signal then you'll also need to gen the OP clock inside the fpga too.